Bistable throttle control system

ABSTRACT

A throttle valve the complete closure of which is prevented by a throttle stop that is advanced be electrically activated vacuum means above a preset speed of an engine responsive to the setting of the throttle valve and retracted below this speed. Pulse generating means connected with the engine provide an input to a timing stage that is operatively connected by capacitor, Zener diode, and amplifier means to means that advance and retract the throttle stop when the speed of the engine is respectively above and below the preset speed.

@15 3,704,382 45] "Nov. 28 1972 United States; Patent Huntzinger IReferences Cited UNITED STATES PATENTS [541 BISTABLE THROTTLEYCONTROLSYSTEM [72] Inventor:

Gerald O. Huntzinger, Anderson, 7

6/1970 Metzler......;..,......,....307/295 Corporation, Primary E,-John- S. Hyeman s AssistantExaminer-R. E. Hatt 7 3 Assignee: GeneralMotors Detroit, Mich.

July 2, 1971 I Attorney-El W. Christen et al.

221 Filed;

I ABSTRACT Appl. No.: 159,270

A throttle valve the complete closure of which is Related us.Application Data [621 Division of Ser. No. 29,1 11,Apri1 16, 19,701

prevented ,by' a' -thro t tle stop that is advanced be electricallyactivated vacuum means above a preset speed of an engineresponsive tothe setting of the throttle valve and retracted belowthis speed. Pulsegenerating 52 us. c1. ..........,.......,307/233, 307/295, 307/271 meansconnected with the engine provide an input to [51] Int. ,...H03k 5/20.307/233, 295, 271; 328/133,

a timing stagev that operatively connected by capacitor, Zener diode,and amplifier means to means that [58] Field ofSearch advance andretract the throttle stop when the speed of the engine'is respectivelyabove and below the preset speed.

2 Claims, 1 Drawing Figure PATENTEDnnv 28 1972 INVENTOR.

Gerda 6? Hzzzrk/ BY 7 M 74% A] TURNEV having electrical meansforactivating utilization means when the speed of an apparatus to becontrolled exceeds a predetermined speed and thereafter deactivatingtheutilization means when the speed of the apparatus returns below thepredetermined limit.

, A specific response is often desired when the speed of an apparatus tobe controlledexceeds a predetermined level and where the responseis'subsequently'to be deactivated when the speed falls below that level.As one example, when the accelerator pedal on a vehicle powered by aninternal combustion engine is released to allow deceleration, it isnevertheless desirable to keep the throttle valve in the-intake of thecarburetor open slightly even though the valve is connected to theaccelerator pedaland would tend to be closed thereby. Aslightly openthrottle valve allows the vacuum maintained by the decelerating engineto continueto .draw air through the carburetor and allow this air to bemixed with fuel stillbeing sucked into the carburetor at a rateproportional to the speed of the engine. Being mixed with the airadmitted through the slightlyopen throttle valve the fuel injected intothe carburetor is then burned more completely since complete combustionis effected more readily with the resulting air fuel mixture than withthe highly rich mixture that might be experienced if the throttle valvewere allowed to close Further, it'is also desirable to allow the valvethat is kept open slightly during engine deceleration to close when theengine speed drops below the predetermined limit. Otherwise,unnecessarily high idle speeds might be maintained thereby possiblyaffecting the engine performance, allowing the engine to stall uponbraking, etc.

Solenoids and other devices for either maintaining throttle valves openduring certain conditions or closing them under other conditions areknown in the art. However, it has not been known heretofore how toemployone system to both keep the throttle open and then allowit to close asthe engine speed first exceeds a predetermined limit and thensubsequently returns below it.

The present system, however, employs a speed sensitive circuit allowingsuch features to be obtained. The circuit is comprised basically of aunijunction transistor configured to be a timing circuit the outputsfrom which are enabled below a predetermined speed and are disabledabove it. Even though pulses having frequency varying with engine speedcould be picked up at other locations, the input to this timing circuitis taken from the breaker points of the distributor in the ignitionsystem for the engine and is applied to the unijunction via first apulse shaping circuit and then an input transistor. If the periodbetween breaker pulses is shorter than that of the period associatedwith predetermined speed, a capacitor connected to both the inputtransistor and the emitter of the unijunction is discharged through theformer before being charged sufficiently to break down the latter. Ifthe period between pulses is longer than that associated with thepredetermined speed, the unijunction is fired at a rate determined bythe capacitor and the reference voltage from which it is charged. Theoutput of the unijunction when thus enabled below the preset speedswitches an inverting transistor to discharge a capacitor connected to aZener diode. When the unijunction is not enabled above the preset speed,the inverting transistor allows the capacitor to charge up to break downthe Zener diode and energize utilization means, here including a windingin a vacuum operated power unit. This causes the tip of a plunger onvacuum operated power unitto arrest the motion of the linkagecontrolling the throttle valve. I

To assure that the timing characteristics of both the capacitor tied tothe emitter of the unijunction and the capacitor tied to the Zener diodein the output stage do not vary with changes in their supply voltages,both capacitors are connected to a voltage supply that is maintainedconstant, here by a Zener diode connected between ground and a conductorconnected 'to the positive terminal of the battery. With an unregulatedreference, the switching frequency of the unijunction might otherwisevary to correspond with a range of frequencies of the device to becontrolled or the output circuit might be deactivated at a speed not thesame as that at which it was activated.

This constant reference not only allows the unijunction to stopswitching and the output stage to cause the throttle stop to advanceprecisely 'when the predetermined frequency is exceeded, but also, andjust as important, it causes the unijunction to start switching and theoutput circuit to cause the throttle stop to retract precisely when thespeed returns below the predetermined frequency. The result is thatthere is no hysteresis between the frequency at which the throttle stopis advanced and that at which it is retracted. The circuit is thereforetermed bi-stable since an output is either effected or not by whetherthe set frequency is exceeded or not. I s

It is, therefore, a general object of the present invention to'provideelectrical means responsive to the actual speed of an engine to preventthe throttle valve of the engine from closing above a predeterminedspeed and allow it to closebelow such speed.

It is another general object of the present inventio to provide a systemof the foregoing type wherein the engine speed above which theelectrical means activate one response from utilization means issubstantially the same speed below which the electrical means deactivatesuch response.

It is a further object of the present invention to provide a frequencysensitive circuit comprised of a timing stage that compares thefrequency of the pulses produced by the apparatus to be controlled witha predetermined frequency and that in turn activates and deactivatesutilization means operatively connected with the apparatus depending onwhether the predetermined frequency is exceeded or not.

It is a further and more specific object of the present invention toprovide a frequency sensitive bi-stable circuit for controlling theadvancement and retraction of the throttle stop of the throttle valve ofan internal combustion engine wherein the difference between thefrequency above which the circuit is activated and the frequency belowwhich it is deactivated is minimized by means of a capacitor and a Zenerdiode connected in I the output stage of the circuit.

These and other objects of the present invention will be apparent fromthe description below taken with reference to:

FIG. 1 wherein a preferred embodiment of the bistable' frequencysensitive circuit is shown connected between the throttle valve andbreaker points of an internal combustion engine.

With reference now to FIG. 1, it may be seen that air for an engine isprovided through an intake passage 12 in carburetor 14 where the airflow is mixed with fuel supplied through an idle port 15 and iscontrolled by.'throttle valve 16. Throttle valve 16 is'pivoted inpassage 12 above port 15 by lever 18 connected to rod 20 which isactivatedby accelerator 22 pivoted on hub 24: mounted to tire wall 26and biased therefrom by spring 2,8. With the depression of pedal 22throttle valve 16 is opened to increase flow to engine 10, and withthcrelease of pedal 22, spring 28 acting on pedal 22 causes rod 20 to movelever 18 so as to close valve 16.

Due to a mechanical linkage 30 between the crankshaft of engine 10 anddistributor cam 31, distributor breaker points 32 are opened and closedat a frequency proportional to speed of the engine 10. With suchoperation of breaker points 32, energy from battery 34 is suppliedthrough ignition switch 36 to primary ignition coil 38, which upon theopening of points 32 induces a voltage in secondary coil 39 connected tothe spark plugs (not shown).

, The voltage pulses induced by this action of the breakers is alsoapplied to frequency sensitivecircuit 40 comprised generally of inputand shaper stage 42, voltage reference and protection stage 44,unijunction timing stage 46, output stage48, and supply conductors 50and 52. Output stage 48 is also operatively connected to a winding 54 inutilization means 55 here in the form of a vacuum power unit 56,throttle stop rod 58, throttle lever 18, throttle valve 16 andcarburetor 14.

input stage 42 is comprised of resistors R1, R2, R3 and R4, diode D1,capacitors C1 and C2, and transistor Q1. The base of transistor 01 isconnected to the node between breaker points 32 and coils 38 and 39,across resistor R1 which attenuates the breaker-induced voltage, acrossforwardly connected diode D1 which protects transistor 01 againstreverse voltages, across resistor R2 and capacitor C1 which filtersignal variations due to speed, coil types, and spark plug conditions,and across resistor R3 which biases the Q1 base. The Q1 collector isconnected to and energized from battery 34 via ignition switch 36,forward diode D2, and resistor R4. The O1 collector is also connected tocapacitor C2 which differentiates the trailing edge of the pulse.thereat to convert the variably-sloped front of the input signal to asharp-edged input pulse suitable for precision timing purposes in thefollowing unijunction timing 46.

Voltage reference and protection stage 44 is comprised generally ofconductors 50 and 52, Zener diodes D3 and D4, capacitor C3, andresistors R5, R6, R7, R8, R9 and R10. Capacitor C3 and resistor R5 actas a filter to prevent high frequency transients in the ignition systemfrom appearing on conductor 50, and Zener diode D3 clamps the potentialof conductor 50 at a constant potential with respect to ground. Variableresistor R7 connected in series with R6 permits the timing ofunijunction timing stage 46 to be adjusted, and resistors R8 and R10provide proper temperature compensation and timing characteristicsrespectively for timing stage 46 and output stage 48. Finally,series-connected Zener D4 and resistor R9 serve to protect semiconductorelements in .output stage 48 from excessive dissipation in the presenceof battery over-voltages, as might be experienced with high-voltagebooster starts.

Unijunction timing stage 46 is comprised of input transistor 02,unijunction transistor Q3, capacitor C4, and resistors R11 and R12, thelatter for respectively biasing the base of Q2 and Q3 with respect toground. The O2 collector and Q3 emitter are commonly connected tocapacitor C4 and also to conductor 50 via series-connected resistors R6and R7. Output stage 48 is comprised of an inverting transistor Q4, aDarlington output pair Q5 and Q6, capacitor C5, diode D5,.and resistorR13. The O4 base is connected to the base of Q3, and the Q4 collector iscommonly connected to one side of capacitor C5 the other side of whichis grounded and to the cathode of Zener D5, the anode of which isconnected to the base of D5 and also to ground across resistor R13.

Vacuum power unit 56 is secured to the housing of carburetor l4 and hasa closable atmospheric port 60, a non-closable atmospheric port 61 andalso vacuum port 62 connected with a vacuum supply by a hose 63. Unit 56also has a coil 54 that is energizable by Darlington pair Q5 and Q6 andis wound to encircle a metallic slug 59 having an atmospheric port 60there-through. Port 60 is scalable at internal end of slug 59 when coil54 is energized to attract armature 64 affixed to flap 66 attached tosealing grommet 68 and resiliently pivoted at pivot 70 so as to openport '60 when coil 54 is deenergized. Also connected to vacuum unit 56by the periphery thereof is a diaphragm 72 having a centrallylocatedthrottle stop rod 58 connected thereto and displaceable with respect tounit 56 through opening 74 therein sealed by ring 75. A spring 76located on rod 58 between the inside of vacuum unit 56 and a collar 78urges the latter to extend from unit 56 when atmospheric port 60 isclosed as the result of the energization of winding 54. Whenwinding 54is de-energized, the internal vacuum aided by the resilient pivot causesflap 66 to open port 60. The tip 80 of rod 58 is then retracted to aposition 80a, shown exaggerated in FIG. 1, where tip 80 does not arrestthe motion of lever 18. When winding 54 is energized the tip 80 of rod58 is extended to position 80b, where it stops lever 18 from attainingthe position otherwise urged by spring 28 acting on rod 20.

The operation of circuit 40 is generally as follows. Pulses of afrequency corresponding with the speed of engine 10 are generated bybreaker points 32, filtered by C1 and R2, and applied to the 01 base.When breakers 32 open, transistor O1 is turned on to ground both the Q1collector and also one side of differentiating capacitor C2. When thebreakers subsequently close, O1 is then turned off and the other side ofcapacitor C2 simultaneously differentiates the falling wave front andapplies the resulting positive spike to the base of transistor Q2,thereby turning it on and providing a discharge path for capacitor C4spike, transistor O2 is turned off again" to allow capacitor C4 tocommence charging to the potential of conductor 50 across resistors R6and 'R7.Capacitor C4 continues to charge until discharged again upon theoccurrence of another pulse generated by breakers 32.

But, if the period between breaker pulses is sufficient,

as when the frequency of the apparatus is below the set point, thecharge on capacitor C4 will increase to attain the voltage required tobreak down unijunction 03sefore the occurrence of the next breakerpulse.

i The set point frequency of the circuit is thus seen to be determinedby the time between successive breaker pulses required to charge up thecapacitor tojbreak down unijunction 03. This set point, moreover, may beincreased by increasing variableresistance R7 to lower the potentialcharging capacitor C4 and in turn increase the C4- charging periodbefore Q3 breakdown. Conversely, the set point frequency may be loweredby decreasing variable resistance R7. Unijunction 03, when it does breakdown, provides an output potential at base one thereof which is appliedacross resistor R12 to the base of transistor 04 to bias Q4 on and simultaneously discharge capacitor C'Stherethrough.

Should the breaker pulses occur at a frequency too great to allowcapacitor C4 to build up sufficiently to break down unijunction Q3,capacitor C would charge up from conductor 50 across resistor R to breakdown Zener D5 and thereby provide a biasing voltage to Darlington pairQ5 and O6 across resistor R13. Current would then be drawn through theQ6 collcctor'to-emitter junction from battery 34, via ignition switch36, diode D2, conductor 52 and coil 54. This would cause flap 66 toclose atmospheric port 60. Diaphragm 72 would then be drawn toward port62 thereby compressing spring 76 acting on collar 78 andextendingthrottle stop rod 58 to retard the motion of lever 18 whenreleased by pedal 22 so as to prevent complete closure of throttle valve16.

Subsequently, when the frequency of the breaker pulses decreases belowthat required to keep unijunction O3 off, the potential at the cathodeof Zener D5 would again be grounded with every second breaker pulsethrough Q4 so that conduction through Zener D5 is blocked, transistor Q6accordingly turned off and coil 54 de-energized. Diode D6 connectedacross conductor 52 and the Q6 collector then provides a discharge pathfor the energy stored in coil 54, thereby protecting Q5 and 06 from theinduced reverse voltages.

The operation of the circuit where the frequency of the breaker pulsesis just at the set point frequency affords further understanding of therole of capacitor C5. If capacitor C5 were not in the circuit, at speedscorresponding to the set point frequency any variations in the periodbetween breaker pulses due to conditions other than changes in enginespeed could break down the Zener D5 intermittently to ultimatelyactivate rod 58. Thus, tooth-to-tooth variations in the dimensions ofthe gears in link 30, in the dimensions of the contiguous surfaces ofcam 31, or in the dimensions of the rubbing arm on the breaker activatedby cam 31 might be sufficient to alter the period between successivepulses to sporadically break down Zener D5 even though the basicfrequency were slightly below the set point. However, by introducingcapacitor C5, the timing action afforded thereby averages out thepulse-to-pulse differences in duration between pulses at the same basicfrequency so that the average duration between pulses at-a basicfrequency is employed to break down Zener D5 rather than the durationbetween any set of successive'pulses;

Thus, a major purpose of capacitor C5 is to average out the effects ofboth manufacturing and wearing tolerances introduced by'the mechanicaland electrical components comprising the path to the gate of unijunctionQ3. Capacitor C5 thereby prevents output circuit 48, and in turn winding54 and rod 58, from being intermittently activated and deactivated forthe first few pulses that occur when speed of apparatus first exceedsthe set point.

For the values of the components employed to construct the circuit shownin FIG. 1 and listed in Table 1 below, the period of averaging at a setpoint frequency of 1300 rpm is approximately 10 pulses allowing cam 31and the linkage 30 driving it to make at least one revolution after theset point frequency has been exceeded before the throttle stop isadvanced. However, changes in the voltage charging capacitor C5 couldproduce variations in the set point frequency offsetting those removedby the action of capacitor C5 in averaging the effects of tolerances inthe mechanical and electrical components. To enable capacitor C5 toperform its function and allow the timing precision of the overallcircuit to be attained without hysteresis, capacitor C5 must also becharged from a constant reference, here the same reference provided forcapacitor C4 by the connection of Zener D3 to battery supply conductor50.

The following table lists the values for types of components that may beemployed to embody the configuration of the invention as shown in FIG.1.

TABLE-OF COMPONENT VALUES AND TYPES FIG. 1

Resistor Ohms Diode Type & Rating R1 3.9K D1 150 PRV Surmetic 2 1.8K 21966808 Surmetic 3 3.9K 3 10 V. Zen'er 4 3.3K 4 20 V. Zener 5 330 5 6.2V. Zener 6 50K 6 1966808 Surmetic 7 25K or 50K Transistor Type 8 1.2K 011968958 NPN 9 1K 2 1968958 NPN 10 15K 3 2Nl67l UJT 11 1K 12 47 4 1968958NPN 13 33K 5 D28Cl Darlington Capacitor Rating C1 0.068 mfd, 100 V. 20.068 mfd. 100 V. 3 20 mfd. 25 V. 4 0.15 mfd, V. 5 4 mfd. 25 V.

tion, it may be desirable to use the speed sensitive circuit to allowthe shift gears in a vehicle transmission to engage at just a certainspeed and to prohibit engageme'nt outside a small range about thisspeed. Such control of gear shifting would be desirable for instancewith high performance machines where the gears might be stressedunnecessarily if engagement were attempted outside the narrow range or,if gear engagement were unsuccessful during shifting, the engine couldbecome unloaded and could therefore tend to run away, possiblydamaging-itself.

In yet another application, it may be desirable to use the circuit'tocontrol the injection of fuel into the combustion chamber of an engineat one rate of change with changesin engine speed up to one speed and atanother rate of change above that speed. The control of the fuelrate/engine speed characteristic thereby afforded would in turn yieldbetter engine performance and more complete combustion of fuel.

lt will be obvious tothose skilled in the art that modifications. andchangesmay be made without departing from. my invention and I,therefore, aim in the appended claims to cover such modifications andchanges as fall within the true spirit and scope of my invention. I i

What l claim as new and desire to secure by letters of patent of theUnited States is: g

l. A bi-stable frequency sensitive circuit receiving an input signalthereto and providing a response therefrom, said circuit connected witha voltage source and comprising:

a. signal generating and shaping means for developing a pulsating signalproportional to said input signal;

b. first timing means having an input connected with said signalgenerating and shaping means and operative in response to said pulsatingsignal for producing at an output a first output when the frequency ofsaid pulsating signal is above a predetermined frequency and a secondoutput when the frequency of said pulsating signal is below saidpredetermined frequency;

c. second timing means comprising a transistor connected with saidoutput of said first timing means to receive said first and secondoutput signals therefrom, a resistor connected with said transistor andsaid source, and a capacitor connected with said resistor, whereby saidcapacitor is charged to a predetermined voltage through said resistorwhen the output of said first timing means is one of said first andsecond output signals and is discharged'through said transistor beforeattaining said predetermined voltage when the output of said firsttiming means is the other of said first and second output signals;

d. a constant impedance breakdown device connected with said capacitorand operative to break down when said capacitor is charged to saidpredetermined voltage; and,

e. utilization means connected with said constant impedance breakdowndevice and operable to produce a response when the output of said firsttiming means is oneof said first and second outputs.

2. A bi-stable frequency sensitive circuit receiving an input signalthereto and providing a response therefrom, said circuit connected witha voltage source and comprising:

a. a source of constant potential;

b. signal generating and shaping means for developing a pulsating signalproportional to said input signal;

c. first timing means comprising a first transistor connected with saidsignal generating and shaping means, a resistor connected with saidsource and said first transistor, a capacitor connected with saidfirsttransistor and said resistor, and a unijunction transistor connectedwith said capacitor, whereby said unijunction transistor produces afirst output when the frequency of said input signal is above apredetermined frequency and a second output-when the frequency of saidinput signal is below said predetermined frequency;

d. second timing means comprising a second transistor connected withsaid unijunction transistor to receive said first and second outputsignals therefrom, a second resistor connected with said secondtransistor and said source, and a second capacitor connected with saidsecond resistor, whereby said second capacitor is charged to apredetermined voltage through said second resistor when the output fromsaid first timing means is one of said first and second output signalsand is discharged through said second transistor before attaining saidpredetermined voltage when the output of said first timing means is theother of said first and second output signals;

e. a constant impedance breakdown device connected with said secondcapacitor and operative to break down when said second capacitor ischarged to said predetermined voltage; and

f. amplifier means connected with said constant impedance breakdowndevice and operable to produce a response when the output of said firsttiming means is one of said first and second outputs.

1. A bi-stable frequency sensitive circuit receiving an input signalthereto and providing a response therefrom, said circuit connected witha voltage source and comprising: a. signal generating and shaping meansfor developing a pulsating signal proportional to said input signal; b.first timing means having an input connected with said signal generatingand shaping means and operative in response to said pulsating signal forproducing at an output a first output when the frequency of saidpulsating signal is above a predetermined frequency and a second outputwhen the frequency of said pulsating signal is below said predeterminedfrequency; c. second timing means comprising a transistor connected withsaid output of said first timing means to receive said first and secondoutput signals therefrom, a resistor connected with said transistor andsaid source, and a capacitor connected with said resistor, whereby saidcapacitor is charged to a predetermined voltage through said resistorwhen the output of said first timing means is one of said first andsecond output signals and is discharged through said transistor beforeattaining said predetermined voltage when the output of said firsttiming means is the other of said first and second output signals; d. aconstant impedance breakdown device connected with said capacitor andoperative to break down when said capacitor is charged to saidpredetermined voltage; and, e. utilization means connected with saidconstant impedance breakdown device and operable to produce a responsewhen the output of said first Timing means is one of said first andsecond outputs.
 2. A bi-stable frequency sensitive circuit receiving aninput signal thereto and providing a response therefrom, said circuitconnected with a voltage source and comprising: a. a source of constantpotential; b. signal generating and shaping means for developing apulsating signal proportional to said input signal; c. first timingmeans comprising a first transistor connected with said signalgenerating and shaping means, a resistor connected with said source andsaid first transistor, a capacitor connected with said first transistorand said resistor, and a unijunction transistor connected with saidcapacitor, whereby said unijunction transistor produces a first outputwhen the frequency of said input signal is above a predeterminedfrequency and a second output when the frequency of said input signal isbelow said predetermined frequency; d. second timing means comprising asecond transistor connected with said unijunction transistor to receivesaid first and second output signals therefrom, a second resistorconnected with said second transistor and said source, and a secondcapacitor connected with said second resistor, whereby said secondcapacitor is charged to a predetermined voltage through said secondresistor when the output from said first timing means is one of saidfirst and second output signals and is discharged through said secondtransistor before attaining said predetermined voltage when the outputof said first timing means is the other of said first and second outputsignals; e. a constant impedance breakdown device connected with saidsecond capacitor and operative to break down when said second capacitoris charged to said predetermined voltage; and f. amplifier meansconnected with said constant impedance breakdown device and operable toproduce a response when the output of said first timing means is one ofsaid first and second outputs.